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ADVANCES IN INDUSTRIAL ENGINEERING AND MANAGEMENT
ISSN:2222-7059 (Print);EISSN: 2222-7067 (Online)
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Title : A Robust Design Optimization Technique for the Low Power CMOS VLSI
Author(s) : Tapas Halder
Author affiliation : Kalyani Government Engineering College, Electrical Engineering Department, Kalyani, West Bengal, PIN-741235, India
Corresponding author img Corresponding author at : Corresponding author img  

Abstract:
The paper depicts on the design optimization skills for the low power CMOS VLSI for the reliable and robust power supply entity to encourage the compactness, faster computation, power loss reductions, uncharacteristic leakages and reduction of the parasitic effects for the wider substitute of the applications. The design textures of the VLSI devices not only strengthen low power consumptions in terms of the power transfer proficiency, dynamic power, static power and the low power designing but also operate in the stable sector inside the solid integrated circuit (IC) as faster software simulation, modeling, commercial success and considerable cost effective solutions.

Key words:CMOS VLSI; power consumption; modeling; analysis; computational speed and results.

Cite it:
Tapas Halder, A Robust Design Optimization Technique for the Low Power CMOS VLSI, Advances in Industrial Engineering and Management, vol. 5, no. 1, 2016, pp. 74-79, doi: 10.7508/aiem.2016.01.015

Full Text : PDF(size: 322.54 kB, pp. 74-79, Download times:182)

DOI : 10.7508/aiem.2016.01.015

References:

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