: Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder
: Advanced VLSI Design Lab, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata, India
The growing pace and complexity of today’s outlines imply a noteworthy rise in the power consumption of very-large-scale integration (VLSI) chips. We all are passionate to give the steadiness in the curve of power consumption day by day. To encounter this problem, researchers have evolved many different design approaches to minimize power. As electronic components are being blended into small, portable gadgets, the requirement increases for growing functionality, with chopped size and slighter power consumption in unit time. This suggests a requirement to stabilize ultra-low power with area-efficient design. In this paper, we explore the implementation of 1-bit full adder using 4:1 Multiplexer in sub-threshold region for ultra-low-power applications in both CMOS logic and ECRL logic. The results of the simulations show that the ECRL logics have some advantages compared to their CMOS logic counterparts of same circuit. Enhancing the execution of these circuits will guide to improvement of gross system performance.
:Full Adder; Multiplexer; Sub-Threshold; CMOS; ECRL; Ultra Low Power
Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder, Design and Analysis of Multiplexer Based CMOS Full Adder in Conventional and Adiabatic Logic for Ultra Low Power Application in Sub-Threshold Regime, Advances in Industrial Engineering and Management, vol. 5, no. 2, 2016, pp. 171-178, doi: 10.7508/aiem.2016.02.001
(size: 476.44 kB, 171-178
, Download times:
G. Ramana murthy, C. Senthilpari, P. Velrajkumar, and Lim tien sze, 2013. A novel design of multiplexer based full-adder cell for power and propagation delay optimizations, journal of engineering science and technology, vol. 8, no. 6, pp. 764–777.
J. M. Rabaey and Pedram, M. 1995. Low power design methodologies. Kluwer Academic Publishers, Boston.
M. Alito and G. Palumbo 2002. Analysis and comparison of the full adder block. IEEE Transactions on VLSI, vol. 10, no. 6, 806823.
R. Shalem, E. John, and L. K. John, 1999. A novel low power energy recovery full adder cell. Proceedings of the Great Lakes Symposium on VLSI, pp. 380-383.
M. Pedram and J. M. Rabaey, 2002. Power aware design methodologies. Kluwer Academic Publishers, Boston.
D. Soudris, C. Piguet, and C. Goutis, 2002. Designing CMOS circuits for low power European low-power initiative for electronic system design. Kluwer Academic Publishers, Boston /Dordrecht /London.
P. J. Song and G. D. Micheli, 1991. Circuit and architecture trade-offs for high speed multiplication. IEEE Journal of SolidState Circuits, vol. 26, no. 9, pp. 1119-1184.
A. P. Chandrakasan and R. W. Brodersen, 1995. Low power digital CMOS design. Kluwer Academic Publishers, Norwell, MA.