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ADVANCES IN INDUSTRIAL ENGINEERING AND MANAGEMENT
ISSN:2222-7059 (Print);EISSN: 2222-7067 (Online)
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Title : Design and Analysis of Multiplexer Based CMOS Full Adder in Conventional and Adiabatic Logic for Ultra Low Power Application in Sub-Threshold Regime
Author(s) : Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder
Author affiliation : Advanced VLSI Design Lab, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata, India
Corresponding author img Corresponding author at : Corresponding author img  

Abstract:
The growing pace and complexity of today’s outlines imply a noteworthy rise in the power consumption of very-large-scale integration (VLSI) chips. We all are passionate to give the steadiness in the curve of power consumption day by day. To encounter this problem, researchers have evolved many different design approaches to minimize power. As electronic components are being blended into small, portable gadgets, the requirement increases for growing functionality, with chopped size and slighter power consumption in unit time. This suggests a requirement to stabilize ultra-low power with area-efficient design. In this paper, we explore the implementation of 1-bit full adder using 4:1 Multiplexer in sub-threshold region for ultra-low-power applications in both CMOS logic and ECRL logic. The results of the simulations show that the ECRL logics have some advantages compared to their CMOS logic counterparts of same circuit. Enhancing the execution of these circuits will guide to improvement of gross system performance.

Key words:Full Adder; Multiplexer; Sub-Threshold; CMOS; ECRL; Ultra Low Power

Cite it:
Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder, Design and Analysis of Multiplexer Based CMOS Full Adder in Conventional and Adiabatic Logic for Ultra Low Power Application in Sub-Threshold Regime, Advances in Industrial Engineering and Management, vol. 5, no. 2, 2016, pp. 171-178, doi: 10.7508/aiem.2016.02.001

Full Text : PDF(size: 476.44 kB, 171-178, Download times:70)

DOI : 10.7508/aiem.2016.02.001

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