: Avik Chakraborty, Angsuman Sarkar
: ECE Department, Bengal Institute of Technology and Management, Bolpur, India
ECE Department, Kalyani Government Engineering College, Kalyani, India
In this paper, a physics-based two-dimensional analytical surface potential model of asymmetric dual material double-gate MOSFET has been developed. The model details the role of various MOSFET parameters such as source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide to influence the surface potential. From the developed expression of surface potential, expression of threshold voltage was derived. Using the analytical model, an investigation about the ability of gate-engineering technique to suppress considered as the most primitive short-channel effects (SCEs) such as the degradation of threshold voltage and Drain Induced Barrier Lowering (DIBL) has been provided.
:Dual-material gate; double-gate; short-channel effects (SCEs); surface potential; DIBL
Avik Chakraborty, Angsuman Sarkar, Two-dimensional analytical model of asymmetric dual material double-gate MOSFET, Advances in Industrial Engineering and Management, vol. 5, no. 2, 2016, pp. 179-182, doi: 10.7508/aiem.2016.02.002
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Y. Taur, 2002. CMOS design near the limit of scaling. IBM J. Res. Dev., vol. 46, no. 2.3, pp. 213-222.
E. J. Nowak, 2002. Maintaining the benefits of CMOS scaling when scaling bogs down, IBM J. Res. Dev., vol. 46, no. 2.3, pp. 169-180.
S. Thompson, P. Packan and M. Bohr, 1998. MOS Scaling: Transistor Challenges for the 21st Century, Intel Technology Journal, vol. 2, no. 3, pp. 1-19.
A. Sarkar, A. K. Das, S. De and C. K. Sarkar, 2012. Effect of gate engineering in double-gate MOSFETs for analog/RF applications, Microelectronics Journal, vol. 43, no. 11, pp. 873–882.
T. K. Chiang, 2009. A New Two-dimensional Analytical Subthreshold Behavior Model for Short-channel Tri-material Gate-stack SOl MOSFET's, Microelectr. Reliab., vol. 49, no. 2, pp. 113-119.
S. M. Biswal, B. Baral, D. De, and A. Sarkar, 2015. Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE, Superlattices Microstruct., vol. 82, pp. 103–112.
V. Kumari, N. Modi, M. Saxena, and M. Gupta, 2015, Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance, IEEE Trans. Electron Devices, vol. 62, no. 7, pp. 2098–2105.