: Arindam Banerjee, Swapan Bhattacharyya, Arpan Deyasi
: Department of ECE, JISCE, Kalyani, West Bengal, India Department of ECE, RCCIIT, Kolkata, West Bengal, India
High speed ALU design for (2^n±m) radix has been reported in this paper. The design has been achieved using the contemporary reconfigurable logic. Here n and m are any positive integer. So far the arithmetic circuit design is concerned; all the architectures have been shown in binary, ternary or quaternary logic. Here we have shown that the conventional logical operations like AND, OR, XOR etc. can be designed in any radix system. Our design follows a generic structure which can be implemented in any radix system. In the proposed design scheme ten arithmetic operations have been incorporated. The design has been verified using Xilinx ISE and implemented using Vertex-7 FPGA.
:ALU; radix; residue; FPGA; reconfigurable logic
Arindam Banerjee, Swapan Bhattacharyya, Arpan Deyasi, High Speed Reconfigurable ALU Design for Radix (2^n±m), Advances in Industrial Engineering and Management, vol. 5, no. 2, 2016, pp. 183-187, doi: 10.7508/aiem.2016.02.003
(size: 580.21 kB, 183-187
, Download times:
C. Lazzari, P. Flores, J. Monteiro, and L. Carro, 2010. A new quaternary FPGA based on a voltage-mode multi-valued circuit”, in Proc. of Int. Conf. on Design, Automation and Test in Europe, March.
S. Purohit, S. R. Chalamalasetti, and M. Margala, 2009. A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic, in Proc. of ACM G.L. Symp. on VLSI, May.
M. Eaton, 2012. Design and Construction of a balanced ternary ALU with potential future cybernetic intelligent systems applications, Int. Conf. on cybernetic Intelligent Systems (CIS), pp. 30-35.
N. Raad and M. M. Mansour, 2011. A Low Power 32-bit Quaternary Tree Adder, Int. Conf. on Energy Aware Computing, pp. 1-2.
H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima, and K. Arimoto, 2007. Design of a Processing Element based on Quaternary Differential Logic for a Multi-core SIMD processor, Int. Symp. on Multiple Valued Logic, pp. 43-45.
A. P. Dhande and V. T. Ingole, 2005. Design And Implementation Of 2 Bit Ternary ALU Slice, Int. Conf. on Sciences of Electronic, Technologies of Information and Telecommunications, Tunisia, March.
Paul Metzgen, 2004. A high performance 32-bit ALU for programmable logic, in Proc. of ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, February.
L. P. Nascimento, 2001. An Automated Tool for Analysis and Design of MVL Digital Circuits”, in Proc. of the 14th Symp. on Integrated circuits and systems design, September.
A. Marshall, T. Stansfield, I. Kostarnov, J. Vuillemin, B. Hutchings, 1999. A reconfigurable arithmetic array for multimedia applications, Proc. of ACM/SIGDA Int. Conf. on Field Programmable Gate Arrays, January.
 F. Buijs, 1992. ALU synthesis from HDL descriptions to optimized multi-level logic, in Proc. of Int. Conf. on European design automation, October.