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ADVANCES IN INDUSTRIAL ENGINEERING AND MANAGEMENT
ISSN:2222-7059 (Print);EISSN: 2222-7067 (Online)
Copyright © 2000- American Scientific Publishers. All Rights Reserved.


Title : An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET
Author(s) : Payel Pandit, Rahul Das, Shramana Chakraborty, Arpan Dasgupta, Atanu Kundu, Chandan K. Sarkar
Author affiliation : 1Department of Electronics and Communication Engineering, Heritage Institute of Technology, Kolkata 700107, India
2Nano Device Simulation Laboratory, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India
Corresponding author img Corresponding author at : Corresponding author img  

Abstract:
In this paper the characteristics of 14 nm Underlap Double Gate (U-DG) NMOSFET with gate stack (GS) with different underlap length are studied. Underlap optimization is the key solution to minimize short channel effects, such as Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL).The underlap length has been optimized based on the on current to off current ratio (ION/IOFF). The RF performance comparison for the devices with 4 nm, 6 nm and 8 nm underlap length is shown in terms of the parameters such as total gate capacitance (Cgg), intrinsic capacitances (Cgs ,Cgd), intrinsic resistances(Rgs , Rgd), transport delay (τm), the unity current gain cut-off frequency (fT) and the maximum frequency of oscillation( fmax).

Key words:Underlap; gatestack; RF analysis; cut-off frequency

Cite it:
Payel Pandit, Rahul Das, Shramana Chakraborty, Arpan Dasgupta, Atanu Kundu, Chandan K. Sarkar, An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET, Advances in Industrial Engineering and Management, vol. 6, no. 1, 2017, pp. 6-10, doi: 10.7508/aiem.2017.01.002

Full Text : PDF(size: 1.12 MB, 6-10, Download times:80)

DOI : 10.7508/aiem.2017.01.002

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