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ADVANCES IN INDUSTRIAL ENGINEERING AND MANAGEMENT
ISSN:2222-7059 (Print);EISSN: 2222-7067 (Online)
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Title : Design of High Speed, Area Optimized and Low Power Arithmetic and Logic Unit
Author(s) : S. Swetha, MD. Afreen Begum
Author affiliation : Department of ECE, CVR College of Engineering, Ibrahimpatnam-501510, India
Corresponding author img Corresponding author at : Corresponding author img  

Abstract:
Optimization of area, delay and power dissipation is the major issue in low voltage and low power applications. GDI-Gate Diffusion Technology is low power digital combinational design. This technology requires less number of transistors compared to conventional CMOS technology. As the number of transistors reduced, then optimization of area and power is achieved. One of the disadvantages of GDI is poor logic swing, which is overcome by modifying this technique. This paper mainly presents the optimized area and low power 8-bit ALU using Modified Gate Diffusion Input Technique. This technique allows a reduction in area, delay and low power dissipation with full logic swing. Full adder is a basic cell in ALU which is designed using XOR-MUX to have an operation with high-speed and low power. The entire design is done using CADENCE Tool in GPDK 90nm and 45nm technology. Power and delay comparison between conventional CMOS, GDI and Modified GDI is also presented.

Key words:GDI; modified GDI; CMOS; full wing; ALU; low power; MUX; ALU

Cite it:
S. Swetha, MD. Afreen Begum, Design of High Speed, Area Optimized and Low Power Arithmetic and Logic Unit, Advances in Industrial Engineering and Management, vol. 6, no. 1, 2017, pp. 26-31, doi: 10.7508/aiem.2017.01.006

Full Text : PDF(size: 737.13 kB, 26-31, Download times:182)

DOI : 10.7508/aiem.2017.01.006

References:
[1] D. Koppad, S. Hiremath, Low Power 1-Bit Full Adder Circuit Using Modified Gate Diffusion Input (GDI) conference on First International micro and nano technologies.
[2] R. uma and P. Davachelvan, Low power and High Speed Adders in Modified gate Diffusion Input Technique Computer Networks & Communications (NetCom).
[3] T. Esther Rani, M. Asha Rani, Dr. Rameshwar rao, 2011. Area Optimized Low Power Arithmetic And Logic Unit” 978-1-4244-8679-3/11/$26.00 ©2011 IEEE.
[4] D. Anitha, K. Manjunatha Chari, 2014. Low Power ALU Design Considering PVT variations. International Journal for Computer Applications, vol. 104, no. 17.
[5] M. Kamaraju, K. Lal Kishore, A. V. N. Tilak, 2010. Power Optimized ALU for Efficient Datapath International Journals for Computer Applications, vol. 11, no. 11.
[6] S. Swetha, 2016. Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input. International Journal for Computer Applications-Volume-145-No 8.
[7] M. Mano Register Transfer and Microoperations Computer System Architecture. Pearson Education

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