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ISSN:2222-7059 (Print);EISSN: 2222-7067 (Online)
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Title : Design of 4 Bit Rotate Left Network at Low Power and Small Delay Using MOS Transistor at 45 nm Channel Length
Author(s) : Surajit Bari, Debashis De, Angsuman Sarkar
Author affiliation : 1ECE Department, Narula Institute of Technology, Agarpara, Kolkata, India
2 Department of CSE, Maulana Abul Kalam Azad University of Technology, West Bengal, Salt Lake, BF-142, Kolkata, India
3ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, India
Corresponding author img Corresponding author at : Corresponding author img  

In this work the design of 4 bit rotate left network with Metal Oxide Semiconductor (MOS) transistor having channel of 45nm has been presented. To report average power consumption and delay of the network the magnitude of the voltage of control signals and signal sources has been diverse from 0.5 V to 1.2 V .The measured value of average power consumption is 19μW and gate delay is 17.3ps at on voltage of 1 volt. The overall circuit has been simulated using Tanner SPICE (T-SPICE) software.

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DOI : 10.7508/aiem.2017.02.012

[1]J. P. Uyemura, 2002. Introduction to VLSI Circuits and Systems, Wiley, India, pp. 421-422.
[2]H. E. Weste, D. Harris and A. Banerjee, 2008. CMOS VLSI Design, Third Edition, Pearson, India, pp. 574-575.
[3]J. M. Rabaey, A. Chandrakasan and B. Nikolic, 2003. Digital Integrated Circuits A Design Perspective, Second Edition, Pearson, India, pp. 213-215.
[4]S. Kang, Y. Lablebici, 2003. CMOS Digital Integrated Circuits Analysis and Design, Third Edition, TMH, New Delhi, pp. 481-496
[5]D. Das, 2010. VLSI Design, Oxford University Press, pp. 93-96
[6]A. Sarkar, S. De, C. K. Sarkar, VLSI Design and EDA Tools, 2011. Scitech Publications , India, pp. 428-456.
[7]B. Nikolic, 2008. Design in the Power Limited Scaling Regime, IEEE Transaction on Electronic Devices, vol. 55, no. 1, pp. 71-83.
[8]P. Saini and R. Mehra, 2012. A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits", International Journal of Advanced Computer Science and Applications, vol. 3, no. 10, pp. 161-168.
[9]R. Gonzalez, B. Gordon and M. A. Horowitz, 1997. Supply and threshold voltage scaling for low power CMOS, IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216.
[10]R. Verma, R. Mehera, 2015. Area Efficient Layout Design Analysis of CMOS Barrrel Shifter, IJSRET, pp. 84-89 March.

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